FPGA Q&A: State Machine

问题

1. 简述状态机的本质和适应的逻辑设计场合。

2. 状态机的基本要素有那些？

3. 两段式、三段式 FSM 描述方法的基本结构如何？

4. FSM 描述何时使用阻塞赋值，何时使用非阻塞赋值？

5. 三段式 FSM 描述的两个 case 结构中判断表达式与当前状态和下一个状态寄存器的对应关系如何。

回答

1. 状态机的本质和适应的逻辑设计场合
状态机（Finite State Machine, FSM）的本质是一种数学模型，通过有限数量的状态来描述系统行为的模型。状态机通过状态转换图或表的形式来表现，通常包括状态、状态转换条件和输出等要素。它适用于需要根据输入条件变化而在不同状态之间转换的逻辑设计场合，如控制单元设计、协议解析、电梯控制、交通灯控制等。

2. 状态机的基本要素
状态机的基本要素包括：
• 状态（State）：系统在某一时刻的状态，表示系统的当前情况。
• 状态转换（Transition）：从一个状态转移到另一个状态的条件。
• 输入（Input）：影响状态转换的外部信号或条件。
• 输出（Output）：状态机在某一状态下的输出信号或行为。
• 初始状态（Initial State）：系统启动时的初始状态。

3. 两段式、三段式 FSM 描述方法的基本结构
• 两段式 FSM（Two-process FSM）：
• 状态寄存器过程（State Register Process）：用于存储当前状态的寄存器，通常在时钟边沿触发下更新当前状态。
• 组合逻辑过程（Combinational Logic Process）：根据当前状态和输入，决定下一状态和输出。
• 三段式 FSM（Three-process FSM）：
• 状态寄存器过程（State Register Process）：存储当前状态，更新当前状态到下一个状态。
• 下一状态逻辑过程（Next State Logic Process）：根据当前状态和输入，决定下一状态。
• 输出逻辑过程（Output Logic Process）：根据当前状态和输入，决定输出信号。

4. FSM 描述何时使用阻塞赋值，何时使用非阻塞赋值
• 阻塞赋值（Blocking Assignment, =）：用于组合逻辑中的赋值。阻塞赋值按顺序执行，适用于描述组合逻辑（如 always @* 语句块）。
• 非阻塞赋值（Non-blocking Assignment, <=）：用于时序逻辑中的赋值。非阻塞赋值在时钟边沿触发后并行执行，适用于描述时序逻辑（如 always @(posedge clk) 语句块），确保在同一个时钟周期内所有赋值是并行生效的。

5. 三段式 FSM 描述的两个 case 结构中判断表达式与当前状态和下一个状态寄存器的对应关系
• 在下一状态逻辑过程（Next State Logic Process）中，case 结构的判断表达式是当前状态（Current State），用于根据当前状态和输入决定下一状态（Next State）。
• 在输出逻辑过程（Output Logic Process）中，case 结构的判断表达式通常也是当前状态（Current State），用于根据当前状态和输入决定输出信号（Output）。
• 状态寄存器过程（State Register Process）则负责在时钟边沿触发时将当前状态更新为下一状态：

Question

1. Briefly describe the essence of state machines and the logical design situations they are suitable for.

2. What are the basic elements of a state machine?

3. What are the basic structures of two-segment and three-segment FSM description methods?

4. When should blocking assignments be used and when should non-blocking assignments be used in FSM descriptions?

5. In the three-segment FSM description, what is the relationship between the judgment expressions in the two case structures and the current state and next state registers?

Answer

1. Essence of Finite State Machine (FSM) and Suitable Logic Design Scenarios
The essence of a Finite State Machine (FSM) is a mathematical model used to design systems with a finite number of states. An FSM describes the behavior of a system by defining states, state transitions, and outputs. It is particularly suitable for logic design scenarios where the system needs to change states based on input conditions, such as in control units, protocol parsing, elevator control, and traffic light control.

2. Basic Elements of FSM
The basic elements of an FSM include:
• State: Represents the current condition of the system at a given time.
• State Transition: Conditions under which the system moves from one state to another.
• Input: External signals or conditions that influence state transitions.
• Output: Signals or behaviors produced by the FSM in a specific state.
• Initial State: The state in which the system starts upon initialization.

3. Basic Structure of Two-process and Three-process FSM Description Methods
• Two-process FSM:
• State Register Process: Stores the current state and updates it based on the next state.
• Combinational Logic Process: Determines the next state and outputs based on the current state and inputs.
• Three-process FSM:
• State Register Process: Stores and updates the current state.
• Next State Logic Process: Determines the next state based on the current state and inputs.
• Output Logic Process: Determines the outputs based on the current state and inputs.

4. When to Use Blocking and Non-blocking Assignments in FSM Descriptions
• Blocking Assignment (=): Used in combinational logic. Blocking assignments are executed sequentially and are suitable for describing combinational logic (e.g., within always @* blocks).
• Non-blocking Assignment (<=): Used in sequential logic. Non-blocking assignments are executed in parallel upon clock edge triggering, making them suitable for describing sequential logic (e.g., within always @(posedge clk) blocks). This ensures that all assignments within the same clock cycle are processed concurrently.

5. Relationship Between Case Structures and State Registers in Three-process FSM Descriptions
• In the Next State Logic Process, the case structure's conditional expression is the current state. It determines the next state based on the current state and inputs.
• In the Output Logic Process, the case structure's conditional expression is also the current state. It determines the output signals based on the current state and inputs.
• The State Register Process is responsible for updating the current state to the next state at the clock edge: